1. Field of the Invention
The present invention relates to an image display device for displaying an image signal responsive
to digital gray-scale data and a method for driving the image display device, and more particularly to the image display device in which lowering of noise and reduction of power consumption are required to be employed in a flat display device typified by a liquid crystal display (LCD) device.
The present application claims priority of Japanese Patent Application No. 2001-236840 filed on Aug. 3, 2001, which is hereby incorporated by reference.
2. Description of the Related Art
A display device in which a screen is created responsive to digital gray-scale data, such as an LCD device, a plasma display, or a like is widely used. By using a conventional LCD device as an example, configurations and operations of a display device will be described below.
FIG. 11 is a schematic block diagram showing an example of configurations of a conventional LCD device 1. FIG. 12 is a schematic block diagram showing an example of configurations of a conventional signal line driving circuit. FIG. 13 is a timing chart showing operations of a display control circuit and the conventional signal line driving circuit employed in the conventional LCD device 1. FIG. 14 is a diagram conceptually explaining a transfer of gray-scale data used in the conventional LCD device 1.
The conventional LCD device 1, as shown in FIG. 11, includes a display control circuit 3, a scanning line driving circuit 5, and a signal line driving circuit 6, all of which are connected to a liquid crystal panel 2. The liquid crystal panel 2 is so configured that a plurality of gate bus lines (scanning lines) 11 is arranged in a horizontal direction and a plurality of data bus lines (signal lines) 12 is arranged in a vertical direction and, moreover, at every point of intersections of the gate bus lines 11 on each row and the data bus lines 12 on each column are arranged pixel electrodes 13, and between each of the pixel electrodes 13 and each of the corresponding data bus lines 12 are formed TFTs (Thin Film Transistors) 14 and the gate at each of the TFTs 14 is connected to the gate bus lines 11. As shown in FIG. 1, one pixel is so configured that a pixel electrode for a red (R) color, a pixel electrode for a green (G) color, and a pixel electrode for a blue (B) color are sequentially arranged in a horizontal direction and each of the (R, G, B) electrodes is connected to a gate bus line 11 and a predetermined number of such the pixel electrodes 13 is arranged along the gate bus line 11 while a predetermined number of the pixel electrodes 13 for a same color is connected along each of the data bus lines 12 in a vertical direction.
In the display control circuit 3, gray-scale data input for each of the R, G, and B colors is properly sorted in such a manner as to correspond to an arrangement of the pixel in the liquid crystal panel 2 and is output as gray-scale data sorted by changing a position of data to the signal line driving circuit 6 and a control signal for driving a scanning line (gate bus line 11) is output to the scanning line driving circuit 5 and a control signal for driving a signal line (data bus line 12) is output to the signal line driving circuit 6.
The conventional signal line driving circuit 6 chiefly includes, as shown in FIG. 12, a shift register 61 being made up of flip-flops F1, F2, F3, F4, . . . , and Fm, a latch signal outputting section (circuit) 62, a data latch 63, a digital/analog converting section (DAC) 64, and an output controlling section 65.
The shift register 61 is so configured that flip-flops F1, F2, F3, F4, . . . , and Fm corresponding to a number of pixels arranged in a horizontal direction in the LCD device 1 are serially connected which sequentially transmits a latch pulse, in response to a clock, to a back stage. The latch signal outputting section 62 includes each of gate circuits G1, G2, G3, G4, . . . , and Gm being connected to an output terminal of each of the flip-flops F1, F2, F3, F4, . . . , and Fm, each of which is turned ON in response to a gate pulse, and outputs a state of an output from each of the corresponding flip-flops F1, F2, F3, F4 . . . , and Fm as latch signals P1, P2, P3, P4, . . . , and Pm, respectively to the data latch 63.
The data latch 63 latches gray-scale data existing at a position corresponding to each of the pixel electrodes 13 in sorted gray-scale data bus to be fed from the display control circuit 3 in accordance with latch signals P1, P2, P3, P4, . . . , and Pm and produces outputs Q1, Q2, Q3, Q4, . . . , and Qm. The DAC 64 performs digital to analog conversion on a gray-scale signal of each of the inputs Q1, Q2, Q3, Q4, . . . , and Qm and produces DC (direct current) voltage outputs D1, D2, D3, D4, . . . , and Dm and outputs them to each of the pixel electrodes 13. The output controlling section 65 is made up of gate circuits H1, H2, H3, H4, . . . , and Hm and outputs, all at once, DC voltage outputs D1, D2, D3, D4, . . . , and Dm, to each of corresponding data bus lines 12 in response to an output control pulse.
Next, operations of the conventional LCD device 1 are briefly described by referring to FIG. 11 and FIG. 12. The image drawing device (not shown) including a personal computer outputs, for example, gray-scale data being made up of a digital signal for each of the R, G, and B colors. The gray-scale data for each of the R, G, and B colors corresponds to a number of gray levels of an image to be displayed, that is, in the case of, for example, 64 gray levels, the gray-scale data is made up of 6 bits of digitized signals. A vertical sync signal serving as a sync signal is output so as to correspond to a display period for each field and a horizontal sync signal is output so as to correspond to a scanning period for each line.
The scanning line driving circuit 5 scans gate bus lines 11 one by one from above to down. The signal line driving circuit 6 controls, based on gray-scale data having a predetermined strength of light, a voltage level of a data bus line 12 being connected to a corresponding pixel, for each of a plurality of pixels which is in a state of selecting a voltage level of a gate bus line 11. This light in an amount corresponding to gray-scale data to transmit through a pixel being connected to a gate bus line 11 being scanned by the scanning line driving circuit 5.
In the LCD device 1, the display control circuit 3, by sorting gray-scale data in such a manner as to be repeated in order of data for R, G, and B colors for every gate bus line 11 in response to each of the input gray-scale data for the R, G, and B colors and to a sync signal, outputs sorted gray-scale data so as to correspond to an arrangement of pixels in the conventional LCD device 1 and outputs a control signal for driving a scanning line (gate bus line 11) to the scanning line driving circuit 5 according to a sync signal and outputs a control signal for driving a signal line (data bus line 12) to the signal line driving circuit 6.
FIG. 13 is a timing chart illustrating operations of the display control circuit 3 and the signal line driving circuit 6 in the conventional LCD device 1. This shows that the display control circuit 3 always outputs pixel data in response to input pixel data and that the signal driving circuit 6 always performs a latch operation of pixel data.
FIG. 14 is a diagram conceptually explaining transfer of gray-scale data in the conventional LCD device 1. In FIG. 14, display image data on each line is expressed in monochrome (in black and white) for simplification of descriptions. In the case of a color image, “□” shows a display image in a color serving as a reference color and having brightness at a level of a color and “▪” shows a display image in a color being different from “□” and having brightness at a level. “0” shows gray-scale data corresponding to image data “▪” and “1” shows gray-scale data corresponding to image data “□”. As shown in FIG. 14, since gray-scale data are all transferred in a vertical direction regardless of whether there is no correlation (for example, between first line and second line) or there is correlation (for example, between second line and third line), much change in data in the gray-scale data bus occurs accordingly.
Thus, in the conventional LCD device 1, input gray-scale data changes in a manner so as to correspond to a change in a signal output for each of pixel electrodes, regardless of existence of correlation in a vertical direction on a display panel (liquid crystal panel) screen and, therefore, problems occur in that an amount of transmittance data in the gray-scale data bus is large which causes an increase in power consumption associated with gray-scale data transmittance and in EMI (Electro Magnetic Interference) caused by a current change in the gray-scale data bus.